Saturday, 25th January 2020

High-speed comms options enable in-life debug and optimisation

UltraSoC has introduced new high-speed communications capabilities within its embedded analytics architecture, supporting debug and performance optimization in datacenters, high-performance computing, AI and storage applications. The addition of PCIe and gigabit Ethernet connectivity gives developers and users access to fine-grained information about the real-world behavior of such products, both in-lab during product development, and in-life after products are deployed in the field.

Ethernet and PCIe are the most common standard communications formats in use in today’s compute-intensive and performance-critical systems. They are therefore a natural choice for transporting the high volumes of data that engineers need to capture and analyze when profiling and optimizing the performance of such systems.

UltraSoC’s on-chip monitoring and analysis infrastructure provides an in-depth, cycle-by-cycle view of the internal operation of any system-on-chip (SoC) – and of the system surrounding it. This provides unmatched insights into the system’s behavior, but can generate large volumes of data. The addition of fast interfaces helps deal with these big data issues in two distinct use cases. First, as part of the development and debug process for new SoC designs, engineers need to capture, record and analyze the internal behavior of their chips – which often contain multiple heterogeneous processor cores.

Second, system designers and users of high-performance systems such as storage and HPC platforms need to optimize overall system performance under real-world conditions both in the lab and in the field. To achieve this they need to understand the real-world behavior and interactions between the many chips within the overall system, and the software running on them.

Both of these use cases can generate very large data sets, which need to be transported quickly and efficiently.

UltraSoC CTO, Gajinder Panesar, commented, “Our customers in HPC, storage and AI are looking for fine-grained, detailed information on the behavior of their chips, and the products they are used in. As our customers and partners develop and deploy processor- and compute-intensive applications, particularly those in AI or ML, it’s essential we enable these applications with fast and efficient access to the information generated on-chip.”

High-speed connectivity augments the existing embedded intelligence and data compression capabilities within the UltraSoC architecture, which includes hardware-level filters and counters, allowing engineers to home in efficiently on the aspects of the system’s behavior that really matter. Despite this high level of on-chip intelligence, hardware-based behavioral monitoring generates significant volumes of data that need to be transported on- and off-chip. UltraSoC is utilizing PCIe (2 Gbps per lane) and gigabit Ethernet (1 Gbps), making it possible for developers and end-users alike to access and analyze data across complex multicore, hyper scale applications – both in the lab and during operation in the field.

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